1. Field of the Invention
The present invention relates to a power-rail electrostatic discharge (ESD) protection circuit. In particular, the present invention relates to a power-rail ESD protection circuit with ultra-low gate leakage.
2. Description of the Prior Art
In CMOS technology, the device dimension of transistor has been scaled toward the nanometer region. As MOS transistors get smaller and the gate oxide gets thinner, tunneling current through the insulator becomes a non-negligible component with a potential impact on circuit operation and performance. More specifically, the high gate current can render standard ESD power clamps non-functional, necessitating modification to existing circuits to minimize sensitivity to the gate leakage.
A power-rail ESD clamp circuit provides a low-impedance path from VDD to VSS for ESD current. FIG. 1 shows the classic RC-triggered power-rail ESD clamp circuit. Under normal circuit operation conditions, the input end of the inverter has a high voltage level. Accordingly, the output end of the inverter has a low voltage level and the clamping device 12 (i.e. the NMOS) is turned off. Once VDD is zapped by a positive ESD stress with VSS grounded, the input end of the inverter initially has a low voltage level relative to that of VDD. Therefore, the output end of the inverter generates a high voltage level and turns the ESD clamping device 12 on to provide a low-impedance path from VDD to VSS to discharge ESD current.
FIG. 2 shows a classic CR-coupled power-rail ESD clamp circuit. These circuits, or a minor variation of them, have been widely used in ESD protection. Key design parameters for such power supply clamp include the clamped voltage on the VDD pad for various ESD models, the layout area, the current drawn during power-up, the quiescent VDD to VSS leakage current, and the immunity to mistriggering during normal operation conditions.
In the circuits shown in FIG. 1 and FIG. 2, the capacitors are formed with metal-oxide-semiconductor field-effect transistors (MOSFETs). To ensure the clamping device 12 is fully-on for the duration of the ESD event, the RC combination in the detecting circuit 14 must have a time constant greater than a specific value (e.g. 1 μs for human-body ESD model). In practice, this necessitates the use of a large area capacitor. However, from an ESD performance point-of-view, this is a wasted area, as the ESD protection level is mainly determined by the size of the clamping device 12.
For advanced technologies with very thin gate oxide. The thinner gate oxide MOS capacitor gets the smaller capacitor area. The thin gate oxide MOS capacitor in the detecting circuit 14 is associated with significant stand-by power consumption because of the large gate tunneling leakage current. Further, the large gate leakage current of the classic RC-triggered power-rail clamp circuit may cause the clamping device 12 mistriggered. Due to these problems, modified power clamps with a low gate leakage are highly desirable. The requirement for an improved power-rail ESD clamp circuit is not just reduction of the capacitor size, but reduction of the gate leakage current at the same time.